The present invention relates to voltage generating circuits and methods, and more particularly, to circuits and methods for generating a voltage greater than a power supply voltage of a semiconductor memory device.
A conventional semiconductor memory device typically includes a plurality of memory cells, with each cell including a capacitor and an NMOS transistor. A gate of the NMOS transistor typically is connected to a word line. When a power supply voltage is applied to the gate of the NMOS transistor, the NMOS transistor is turned on, so that a ground voltage is transmitted without a loss in threshold voltage, while a power supply voltage is transmitted with a loss in threshold voltage. To transmit a power supply voltage without a loss in threshold voltage, a voltage higher than the power supply voltage typically is applied to the gate. In general, the high voltage is set to be greater than a threshold voltage of the NMOS transistor, added to a power supply voltage. The semiconductor memory device typically includes a high voltage generating circuit for generating the high voltage.
FIG. 1 is a diagram showing a conventional high voltage generating circuit. The high voltage generating circuit includes a high-voltage level detector 10, a control signal generator 12, and a high voltage generator 14. The high voltage generator 14 is composed of capacitors C1-C4 and switches SW1-SW8. Operations of the respective components shown in FIG. 1 will now be described.
The high-voltage level detector 10 detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator 12 drives the precharge signal P1 and pump signals P2-P4 in response to the high-voltage level detection signal VPPEN. The switches SW1, SW2, SW3, and SW6 precharge each of nodes n1, n2, n3, and n4 to a voltage VDD in response to the precharge signal P1. The capacitors C1 and C2 pump the nodes n1 and n2, respectively, in response to the pump signal P2. The capacitor C3 pumps the node n3 in response to the pump signal P3, and the capacitor C4 pumps the node 4 in response to the pump signal P4. The switch SW4 is turned on in response to the pump signal P2 and allows charge to be shared between the nodes n2 and n3, and the switch SW5 is turned on in response to the pump signal P2 and allows charge to be shared between the nodes n1 and n4. The switch SW7 is turned on in response to the pump signal P3 and allows charge to be shared between the nodes n3 and n4. The switch SW8 is turned on in response to the pump signal P4 and allows charge to be shared between the node n4 and a high voltage generating terminal n5.
FIG. 2 is a timing diagram illustrating operations of the high voltage generating circuit shown in FIG. 1. When the control signal generator 12 drives the precharge signal P1 to a high level for a precharge period T1, the switches SW1, SW2, SW3, and SW6 are turned on so that the nodes n1 to n4 are precharged to a power supply voltage VDD.
When the control signal generator 12 drives the pump signal P2 to a high level during a first pumping period T2, the capacitors C1 and C2 pump the nodes n1 and n2 to a voltage 2 VDD. The switch SW4 and SW5 are turned on in response to the high level of the pump signal P2, so that charge is shared between the nodes n1 and n4 and between the nodes n2 and n3, respectively. Thus, the nodes n1-n4 reach a voltage 1.5 VDD.
When the control signal generator 12 drives the pump signal P3 to a high level during a second pumping period T3, the capacitor C3 pumps the node n3 to a voltage 2.5 VDD. The switch SW7 is turned on in response to the high level of the pump signal P3, so that charge is shared between the nodes n3 and n4. Thus, the nodes n3 and n4 reach a voltage 2 VDD.
When the control signal generator 12 drives the pump signal P4 to a high level during a third pumping period T4, the capacitor C4 pumps the node n4 to a voltage 3 VDD. The switch SW8 is turned on in response to the high level of the pump signal P4, so that charge is shared between the node n4 and the high voltage generating terminal n5. Thus, the node n4 and the high voltage generating terminal n5 are pumped to a voltage α. In this manner, the high voltage generating terminal n5 can reach a maximum voltage 3 VDD. The high voltage generating circuit shown in FIG. 1 includes four pumping capacitors C1-C4 and performs a three-stage pumping operation to produce a maximum voltage 3 VDD.
FIG. 3 is a diagram showing another conventional high voltage generating circuit. The high voltage generating circuit includes a high-voltage level detector 20, a control signal generator 22, and a high voltage generator 24. The high voltage generator 24 includes capacitors C5 and C6 and switches SW10-SW15. Functions of the respective components shown in FIG. 3 will now be described.
The high-voltage level detector 20 detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator 22 drives the precharge signal P1 and a pump signal P2 in response to the high-voltage level detection signal. The switches SW10, SW11, SW13, and SW14 precharge nodes n5 and n7 to a ground voltage in response to the precharge signal P1 and precharge nodes n6 and n8 to a power supply voltage VDD. The switch SW12 connects the nodes n6 and n7 in response to the pump signal P2, and the switch SW15 connects the node n8 and a high voltage generating terminal n9 in response to the pump signal P2.
FIG. 4 is a timing diagram illustrating operations of the high voltage generating circuit shown in FIG. 3. When the control signal generator 22 drives the precharge signal P1 to a high level during a precharge period T1, all the switches SW10, SW11, SW13, and SW14 are turned on so that the nodes n5 and n7 are precharged to a ground voltage and the nodes n6 and n8 are precharged to a power supply voltage VDD. When the control signal generator 22 drives the pump signal P2 to a high level during a pumping period T2, the node n5 reaches a power supply voltage VDD, and the capacitor C5 pumps the node n6 to a voltage 2 VDD. Because the switch SW12 is turned on, the node n7 reaches a voltage 2 VDD like the node n6, and the capacitor C6 pumps the node n8 to a voltage 3 VDD. Because the switch SW15 is turned on, charge is shared between the node n8 and a high voltage generating terminal n9, so that the node n8 and the high voltage generating terminal n9 are pumped to a voltage α. In this manner, the high voltage generating terminal n9 may reach a maximum voltage 3 VDD. That is, the high voltage generating circuit shown in FIG. 3 includes two pumping capacitors C5 and C6 and performs a single pumping operation to produce a maximum voltage 3 VDD. Accordingly, the high voltage generating circuit shown in FIG. 3 includes fewer pumping capacitors than the high voltage generating circuit shown in FIG. 1 and may generate a target high voltage with a single pumping operation.
However, semiconductor memory devices generally are being designed with increasingly lower power supply voltage and faster operation as semiconductor manufacturing technologies progress. If a target level for a high voltage decreases, a conventional high voltage generating circuit may be used to generate the target high voltage. However, as power supply voltage decreases, decreases in high voltage may be limited, because the threshold voltage of an NMOS transistor generally cannot be decreased below a certain value. Also, because the period of a high-voltage level detection signal is shortened due to high-speed operation, it is desirable to reduce the number of pumping operations needed to generate a high voltage. Therefore, it is desirable to provide a high voltage generating circuit having excellent pumping capability without an undue number of pumping operations.